BL702/704/706 Reference Manual
6.4.3 Peripheral to memory
In this working mode, when the source peripheral request is triggered, the source configuration is burst to the buffer
until the set number of moves reaches the stop. On the other hand, when the internal cache is enough for the target
burst number once, the DMA will automatically move the cached content to the target address until it reaches the set
number of moves and automatically returns to the idle state, waiting for the next startup
The specific configuration process is as follows:
1. Set the value of the register DMA_C0SrcAddr to the source peripheral address
2. Set the value of the register DMA_C0DstAddr to the target memory address
3. Select the transfer mode and set the value of the DMA_C0Config [FLOWCTRL] bit to 2 to select the Peripheral-
to-memory mode
4. Set the value of the corresponding bit in the DMA_C0Control register: the DI bit is set to 1 to enable the address
auto-accumulation mode, and the SI bit is set to 0 to disable the address auto-accumulation mode , the DTW and
STW bits set the transmission width of the source and destination respectively, and the DBS and SBS bits set the
burst type of the source and destination respectively
5. Select the appropriate channel, enable DMA, and complete the data transfer
6.4.4 Peripheral to peripheral
In this working mode, when the source peripheral requests a trigger, the source configuration burst will be stored in
the buffer, and it will stop until the set number of moves is reached. On the other hand, when the internal cache is
enough for the target burst number, DMA will automatically move the cached content to the target address until the
set number of transfers is reached and automatically return to the idle state, waiting for the next start
The specific configuration process is as follows:
1. Set the value of the register DMA_C0SrcAddr to the peripheral address of the source
2. Set the value of the register DMA_C0DstAddr to the target peripheral address
3. Select the transfer mode, set the value of the register DMA_C0Config[FLOWCTRL] bit to 3, that is, select the
Peripheral-to-Peripheral mode
4. Set the value of the corresponding bit in the DMA_C0Control register: DI and SI bits are set to 0, the address
automatic accumulation mode is disabled, the STW and DTW bits respectively set the source and target transfer
widths, and the SBS and DBS bits respectively set the source and target bursts type.
5. Select the appropriate channel, enable DMA, and complete the data transfer
BL702/704/706 Reference Manual 126/ 375
@2021 Bouffalo Lab
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