Bouffalo Lab BL702 - Page 127

BL702/704/706 Reference Manual
6.5 Register description
Name
Description
DMA_IntStatus Interrupt status
DMA_IntTCStatus Interrupt terminal count request status
DMA_IntTCClear Terminal count request clear
DMA_IntErrorStatus Interrupt error status
DMA_IntErrClr Interrupt error clear
DMA_RawIntTCStatus Status of the terminal count interrupt prior to masking
DMA_RawIntErrorStatus Status of the error interrupt prior to masking
DMA_EnbldChns Channel enable status
DMA_SoftBReq Software burst request
DMA_SoftSReq Software single request
DMA_SoftLBReq Software last burst request
DMA_SoftLSReq Software last single request
DMA_Config DMA general configuration
DMA_Sync DMA request asynchronous setting
DMA_C0SrcAddr Channel DMA source address
DMA_C0DstAddr Channel DMA Destination address
DMA_C0LLI Channel DMA link list
DMA_C0Control Channel DMA bus control
DMA_C0Config Channel DMA configuration
DMA_C1SrcAddr Channel DMA source address
DMA_C1DstAddr Channel DMA Destination address
DMA_C1LLI Channel DMA link list
DMA_C1Control Channel DMA bus control
DMA_C1Config Channel DMA configuration
DMA_C2SrcAddr Channel DMA source address
DMA_C2DstAddr Channel DMA Destination address
DMA_C2LLI Channel DMA link list
DMA_C2Control Channel DMA bus control
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