Bouffalo Lab BL702 - Page 134

BL702/704/706 Reference Manual
Bits
Name Type Reset Description
31:0 DSLFDRS R/W 0 DMA synchronization logic for DMA request signals: 0 =
enable, 1 = disable
6.5.15 DMA_C0SrcAddr
Address：0x4000c100
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMASA
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMASA
Bits
Name Type Reset Description
31:0 DMASA R/W 0 DMA source address
6.5.16 DMA_C0DstAddr
Address：0x4000c104
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMADA
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMADA
Bits
Name Type Reset Description
31:0 DMADA R/W 0 DMA Destination address
6.5.17 DMA_C0LLI
Address：0x4000c108
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLLI
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLLI
BL702/704/706 Reference Manual 134/ 375
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