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BL702/704/706 Reference Manual
6.5.12 DMA_SoftLSReq
Address0x4000c02c
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLSR
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SLSR
Bits
Name Type Reset Description
31:0 SLSR R/W 0 Software last single request
6.5.13 DMA_Config
Address0x4000c030
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD AHB
MEC
SDMA
EN
Bits
Name Type Reset Description
31:2 RSVD
1 AHBMEC R/W 0 AHB Master endianness configuration: 0 = little-endian, 1
= big-endian
0 SDMAEN R/W 0 SMDMA Enable.
6.5.14 DMA_Sync
Address0x4000c034
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DSLFDRS
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DSLFDRS
BL702/704/706 Reference Manual 133/ 375
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