BL702/704/706 Reference Manual
10.4.16 uart_fifo_config_1
Address:0x4000a084
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD RFITH RSVD TFITH
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFICNT TFICNT
Bits
Name Type Reset Description
31 RSVD
30:24 RFITH R/W 7’d0 RX FIFO threshold, dma_rx_req will not be asserted if tx_-
fifo_cnt is less than this value
23 RSVD
22:16 TFITH R/W 7’d0 TX FIFO threshold, dma_tx_req will not be asserted if tx_-
fifo_cnt is less than this value
15:8 RFICNT R 8’d0 RX FIFO available count
7:0 TFICNT R 8’d128 TX FIFO available count
10.4.17 uart_fifo_wdata
Address:0x4000a088
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD UFIWD
Bits
Name Type Reset Description
31:8 RSVD
7:0 UFIWD W x UART FIFO write data
BL702/704/706 Reference Manual 205/ 375
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