Bouffalo Lab BL702 - Page 204

BL702/704/706 Reference Manual
10.4.14 sts_urx_abr_prd
Address：0x4000a034
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ABRPRD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRPRDS
Bits
Name Type Reset Description
31:16 ABRPRD R 16’d0 Bit period of Auto Baud Rate detection using codeword
0x55
15:0 ABRPRDS R 16’d0 Bit period of Auto Baud Rate detection using START bit
10.4.15 uart_fifo_config_0
Address：0x4000a080
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD RFIU RFIO TFIU TFIO RFI
CLR
TFI
CLR
UDR
EN
UDT
EN
Bits
Name Type Reset Description
31:8 RSVD
7 RFIU R 1’b0 Underflow flag of RX FIFO, can be cleared by rx_fifo_clr
6 RFIO R 1’b0 Overflow flag of RX FIFO, can be cleared by rx_fifo_clr
5 TFIU R 1’b0 Underflow flag of TX FIFO, can be cleared by tx_fifo_clr
4 TFIO R 1’b0 Overflow flag of TX FIFO, can be cleared by tx_fifo_clr
3 RFICLR W1C 1’b0 Clear signal of RX FIFO
2 TFICLR W1C 1’b0 Clear signal of TX FIFO
1 UDREN R/W 1’b0 Enable signal of dma_rx_req/ack interface
0 UDTEN R/W 1’b0 Enable signal of dma_tx_req/ack interface
BL702/704/706 Reference Manual 204/ 375
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