BL702/704/706 Reference Manual
Bits
Name Type Reset Description
11:8 SPL R/W 4’h2 ”SPL” sample period in [us/sample]. The SAMPLE register
will be updated for every new sample (at 1MHz)
0: 32 us
1: 64
2: 128
3: 256
4: 512
5: 1 ms
6: 2
7: 4
8: 8
9: 16
A: 32
B: 65
C: 131
7:4 DEGCNT R/W 0 deglitch strength
3 DEGEN R/W 0 deglitch enable
2 LEDPOL R/W 1 qdec led polarity
1 LEDEN R/W 0 qdec led enable
0 QDECEN R/W 0 qdec enable
14.4.2 qdec0_ctrl1
Address:0x4000a804
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD LEDPED
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD IS RPT SPL ACC
Bits
Name Type Reset Description
31:25 RSVD
24:16 LEDPED R/W 0 Period in us the LED is switched on prior to sampling
15:4 RSVD
3 IS R/W 0 input a/b swap
2 RPT R/W 0 rpt option 0: Count time only if sample change 1: Continue
time
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