BL702/704/706 Reference Manual
19.3.2 Wakeup source
The chip supports multiple wake-up sources and can wake up from different power modes.
The CPU will not reset after the PDS0/1/2/3 mode wakes up, and the CPU will reset after the PDS4/5/6/7/31 and
HBN0/1/2 modes wake up. After the CPU wakes up and resets, it can be learned from the event register that it is
currently reset for what reason.
Each power domain has its own wake-up source, the wake-up source in the sleep hibernation state is the sum of the
wake-up sources of the power domain that are still powered in this mode.
PD_AON has the following wake-up sources:
• always on pin wakeup (GPIO9~12)
PD_AON_HBNRTC has the following wake-up sources:
• hbn rtc timer wakeup
PD_AON_HBNCORE has the following wake-up sources:
• pir interrupt, bor interrupt, acomp0 interrupt, acomp1 interrupt
PD_CORE has the following wake-up sources:
• ble sleep timer wakeup、GPIO0~7 Pin Wakeup (select one)、pds timer wakeup
PD_CORE_MISC_DIG and PD_CORE_MISC_ANA have the following wake-up sources:
• kys interrupt、irrx interrupt、GPIO0~8 GPIO Pin Wakeup、GPIO14~31 GPIO Pin Wakeup
PD_USB has the following wake-up sources:
• usb wakeup interrupt
19.3.3 Power mode
Operating mode
The chip provides independent clock control of the processor and peripherals. The clock control of each module is
introduced in the chapter of GLB and clock.
The software can control the clocks of the processors or peripherals that do not need to be used according to the
current application scenarios. The reaction of the clock control is real-time. In this working mode, there is no need to
worry about the response time.
Sleep mode(PDS)
The power-down mode has lower power consumption than the working mode. After entering the PDS mode, control
the clock other than RTC (Real Time Clock), switch to the internal low-speed clock, and turn off the external crystal
oscillator and PLL to achieve a more power-saving state, so entering and leaving this low-power mode will There is a
BL702/704/706 Reference Manual 352/ 375
@2021 Bouffalo Lab
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