Eaton SmartWire-DT SWD Series - Page 139

5 Connection PKE-SWD for motor-protective circuit-breaker PKE12/32/65
5.10 Programming
SmartWire-DT module IP20 01/20 MN05006001Z-EN www.eaton.com 135
Table 21: Bit array XTUA
5.10.1.9 Time delay setting (CLASS)
The CLASS bit field shows the value of the setting dial on the PKE trip block
for the time lag class of the overload release. The setting points of the time
lag class dial are assigned to the following values of the CLASS bit field.
Table 22: Bit array CLASS
5.10.1.10 Remote tripping, PKE basic device (R-TRIP)
Remote tripping of the PKE basic device through output bit R-TRIP causes a
trip if a phase current of at least 85 percent of the minimum mark of the vari-
able overload release on the PKE trip block flows through all three main cir-
cuits (for example PKE-XTUA
-4 ￫ I
min
= 0.85 × 1A = 0.85 A). The maximum
duration of the tripping process from the time the PKE-SWD receives the trip
signal to the actual time of tripping of the PKE basic device is 700 ms.
Field Value Control option part
no.
XTUA 0x0 PKE-XTUA-1.2
0x1 PKE-XTUA-4
0x2 PKE-XTUA-12
0x3 PKE-XTUA-32
0x4 PKE-XTUWA-32
0x5 PKE-XTUA-65
0x6 Not defined
0x7 Not defined
￫
The TYPE bit array XTUA can be read as an acyclical data object
(￫ Section 5.10.3, „Acyclic data“, page 136).
Field Value Set time lag
CLASS 0x0 Class 5
0x1 Class 10
0x2 Class 15
0x3 Class 20
0x4 Test position
0x5 Not defined
0x6 Not defined
0x7 Not defined