Epson TM-U950 - Page 79

2-34 Mechanism Configuration and Operating Principles Rev. A
❏ As print buffer for pattern data to be sent to the print head
❏ As storage area for CPU processing functions (flags, pointers, etc.)
EEPROM
The EEPROM stores the slip paper insert sensor level. Data exchange with the CPU is performed
via a serial link.
Gate array
The gate array is a five I/O port type with an eight-bit (see Table 2-2). It serves two purposes. It
can be used by the CPU for I/O port expansion, as specified in the memory map (port expansion
function). When the ALE signal goes high, the gate array also latches to the multiplexed
address/data signal output by the CPU and extracts the address signal (address latch function).
Table 2-2. Gate Array Pin Assignments
Pin number Gate array function Signal designation` I/O Level Description
1(RSET
)(RSET) I TTL Reset signal input L = reset
2 PA 0 HEAD 8 O TTL Print head 8 L = ON
3 PA 1 HEAD 7 O TTL Print head 7 L = ON
4 PA 2 HEAD 6 O TTL Print head 6 L = ON
5 PC 6 JN_LED O TTL Print head 5 L = ON
6 PA 3 HEAD 5 O TTL Print head 4 L = ON
7 PA 4 HEAD 4 O TTL Print head 3 L = ON
8 PA 5 HEAD 3 O TTL Print head 2 L = ON
9 PA 6 HEAD 2 O TTL Print head 1 L = ON
10 PA 7 HEAD 1 O TTL Print head 0 L = ON
11 GND - - GND Power supply
12 PB 0 SW1I I TTL DIP switch bank 1 serial input
13 PB 1 SW2I I TTL DIP switch bank 1 serial input
14 PB 2 SWCK I TTL DIP switch settings read clock
15 PB 3 SWSL I TTL DIP switch bank select
16 PB 4 SCB O TTL S/J switching solenoid drive signal L = drive
17 PB 5 S/J HL O TTL S/J switching solenoid hold signal L = hold
18 PB 6 HD_COM O TTL Print head common L = ON
19 PB 7 HEAD 9 O TTL Print head L = ON
20 PC 0 E2DI I TTL Data input from EEROM
21 PC 1 E2DO O TTL Data output from EEROM
22 PC 2 E2CK O TTL EEROM select output
23 PC 3 E2CE O TTL EEROM select output
24 PC 4 IMDSR I TTL
DSR signal input from the IM-403/405 serial
interface (unused on the TM-U950P)
CONFIDENTIAL