2-42 Mechanism Configuration and Operating Principles Rev. A
The HDBC signal is a head current limiter. When the head current duration exceeds 0.1s due to
an error, this signal turns the head off. The limit time is determined by C20 and R44 and
retriggered at the falling edge of the HD_COM signal.
Head temperature is measured by feeding the voltage divided by the thermistor and R134 to the
CPU via the analog port AN1.
Figure 2-51. Print Head Timing Chart
Figure 2-52. Print Head Drive Circuit
CONFIDENTIAL
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