GW Instek PEL-2002 - Ese; Esr; Idn; Opc

COMMAND DETAILS
25
*ESE
Status Command
Description
The Standard Event Status Enable command
determines which events in the Standard Event
Status Event register can set the Event Summary
Bit (ESB) of the Status Byte register. Any bit
positions set to 1 enable the corresponding event.
Any enabled events set bit 5 (ESB) of the Status
Byte register. See page138.
Syntax *ESE <NRf>
Parameter <NRf> Bit(s) Set <NRf> Bit(s) Set
4 QYE 32 CME
8 DDE 64 ~
16 EXE 128 ~
Example *ESE 40 Sets CME and DDE events
in the Standard Event
Status Event Register.
Query Syntax *ESE?
Return Parameter <NR1> Bit(s) Set <NR1> Bit(s) Set
4 QYE 32 CME
QYE
8 DDE 64 ~
16 EXE 128 ~
Example *ESE?
40
Returns the settings in the
Standard Event Status
Enable Register. Here CME
and QYE are enabled.
*ESR?
Status Command
Description
Reads the Standard Event Status Register. This
command also clears the Standard Event Status
Register. Page137.
Query Syntax *ESR?
PEL-2000 Programming Manual
26
Return Parameter
<NR1> Bit(s) Set <NR1> Bit(s) Set
4 QYE 32 CME
8 DDE 64 ~
16 EXE 128 ~
Example *ESR?
48
The return value is the
status reading of the
standard Event Status
Register.
*IDN?
System Command
Description
Returns the load generator identification.
Query Syntax *IDN?
Return Parameter <aard> Data <aard> Data
GW
Manufacturer
XXXXXXXX Serial No.
PEL-2000 Model V1.00 Firmware
Version
Example *IDN?
GW, PEL-2002/2004,
00000001, V1.00
Returns the mainframe
identification string.
*OPC
Status Command
Description
This command sets the OPC (Operation Command
Bit) bit (bit 0) of the Standard Event Status Register
after the mainframe has completed all pending
operations. Page137.
Syntax *OPC
Example *OPC
Sets the OPC bit.
Query Syntax *OPC?
Return Parameter <NR1> Operation <NR1> Operation
0 Pending 1 Complete