STATUS REGISTERS
137
Standard Event Status
Description
The Standard Event Status Registers indicate any
programming errors that occur. The Standard
Event Status Register group comprises of the Event
and Enable registers.
Error Bits
OPC The operation complete bit is set when all
selected pending operations are
complete. This bit is set in response to the
*OPC command.
QYE The Query Error bit is set is response to
an error reading the Output Queue. This
can be caused by trying to read the
Output Queue when there is no data
present.
DDE The Device Dependent Error indicates a
memory error/lost memory or failure of
the self-test.
EXE The Execution bit indicates an execution
error due to one of the following
Illegal command parameter
Parameter out of range
Invalid parameter
Command didn’t execute due to an
overriding operation condition.
PEL-2000 Programming Manual
138
CME The Command Error bit is set when a
syntax error has occurred. The CME bit
can also be set when a <GET> command
is received within a program message.
(Group Execute Trigger) as defined in
IEEE 488.1.
Event Register
The Event Register will be set to 0 when read.
Enable Register
The Enable Register determines which events will
set the ESB Bit (bit 5) in the Status Byte Register.
Status Byte Register
Description
The Status Byte register consolidates the status
events of all the status registers. The Status Byte
register can be read with the *STB? query or a
serial poll and can be cleared with the *CLS
command.
Status Bits
CSUM The CSUM bit is set when an Enabled
event has occurred on a channel. The
Channel Condition, Channel Event and
Channel Summary Event Registers all
determine if the CSUM bit is set.
QUES The Questionable bit is set when a
questionable event has occurred.
MAV The Message Available bit is set when
there is outstanding data in the Output
Queue.
ESB The Event Status bit is set if an enabled
event in the Standard Event Status Event
Register has occurred.
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