B 4237-1/-2 / H41q-HS/HRS (0605)
81
– 2 interfaces RS 485 with galvanic isolation. Transmission rate: max. 57600 bps
– 4digit diagnostic display and 2 LEDs for information out of the system, I/O level and user
program
– Dual Port RAM for fast memory access to the second central module
– Hardware clock, battery buffered
– I/O bus logic and connection to the input/output modules
– Watchdog
– Power supply monitoring, testable (5 V system voltage)
– Battery monitoring
2.2 Coprocessor module F 8621A
Right of the central module of the H41q-HS/HRS PES respectively one coprocessor module
can be installed. The coprocessor module mainly contains:
– Microprocessor HD 64180 with a clock frequency of 10 MHz
– Operating system EPROM
– RAM for a PLC master project
– Two interfaces RS 485, via communication software function block setting of the baud rate
up to 57600 bps
– Dual port RAM (DPR) for the communication with the central module via CPU bus
2.3 Communication modules F 8627/F 8628, F 8627X/F 8628X
Right of the central module of the H41q-HS/HRS PES respectively one communication module
can be installed. The communication module mainly contains:
– 32-bit RISC microprocessor
– Operating system
– RAM for further protocols
– F 8627 Ethernet interface (safeethernet, OPC, ...)
F 8628 Profibus-DP slave interface
– Dual port RAM (DPR) for the communication with the central module via CPU bus
Special applications with the communication module F 8627X:
– connection of the central module to a PADT (ELOP II TCP)
– connection to other communication partners within an Ethernet network (Modbus TCP)
Special application with the communication module F 8628X:
– ELOP II TCP connection (PADT) via the Ethernet interface of the F 8628X to the H41q/
H51q controller
3 Startup and maintenance
A battery change of the buffer batteries without load (CPU in operation) is recommended every
6 years.
Buffer battery with soldering lug: HIMA part no. 44 0000016.
Buffer battery without soldering lug: HIMA part no. 44 0000019.
Further informations see also catalog H41q/H51q, chapter 9, "Startup and maintenance".
Note The RAM for the master project is buffered via the batteries on the
backplane of the subrack.
Before startup the system switch on the rear buffer batteries G1 and
G2 via DIP switches on the backplane!