EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
4-50
4.4 ENHANCED BUS MODE OPERATION (WRITE-BACK MODE) FOR THE
WRITE-BACK ENHANCED IntelDX4™ PROCESSOR
All Intel486™ processors operate in Standard Bus (write-through) mode. However, when the in-
ternal cache of the Write-Back Enhanced IntelDX4 processor is configured in write-back mode,
the processor bus operates in the Enhanced Bus mode. This section describes how the Write-Back
Enhanced Intel486 processor bus operation changes for the Enhanced Bus mode when the inter-
nal cache is configured in write-back mode.
4.4.1 Summary of Bus Differences
The following is a list of the differences between the Enhanced Bus and Standard Bus modes. In
Enhanced Bus mode:
1. Burst write capability is extended to four doubleword burst cycles (for write-back cycles
only).
2. Four new signals: INV, WB/WT#, HITM#, and CACHE#, have been added to support the
write-back operation of the internal cache. These signals function the same as the
equivalent signals on the Pentium
®
OverDrive
®
processor pins.
3. The SRESET signal has been modified so that it does not write back, invalidate, or disable
the cache. Special test modes are also not initiated through SRESET.
4. The FLUSH# signal behaves the same as the WBINVD instruction. Upon assertion,
FLUSH# writes back all modified lines, invalidates the cache, and issues two special bus
cycles.
5. The PLOCK# signal remains deasserted.
4.4.2 Burst Cycles
Figure 4-37 shows a basic burst read cycle of the Write-Back Enhanced IntelDX4 processor. In
the Enhanced Bus mode, both PCD and CACHE# are asserted if the cycle is internally cacheable.
The Write-Back Enhanced IntelDX4 processor samples KEN# in the clock before the first
BRDY#. If KEN# is asserted by the system, this cycle is transformed into a multiple-transfer cy-
cle. With each data item returned from external memory, the data is “cached” only if KEN# is
asserted again in the clock before the last BRDY# signal. Data is sampled only in the clock in
which BRDY# is asserted. If the data is not sent to the processor every clock, it causes a “slow
burst” cycle.
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