Intel Embedded Intel486 User Manual

EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
4-54
4.4.3.1 Snoop Collision with a Current Cache Line Operation
The system can also perform snooping concurrent with a cache access and may collide with a cur-
rent cache bus cycle. Table 4-12 lists some scenarios and the results of a snoop operation collid-
ing with an on-going cache fill or replacement cycle.
4.4.3.2 Snoop under AHOLD
Snooping under AHOLD begins by asserting AHOLD to force the Write-Back Enhanced
IntelDX4 processor to float the address bus, as shown in Figure 4-38. The ADS# for the write-
back cycle is guaranteed to occur no sooner than the second clock following the assertion of
HITM# (i.e., there is a dead clock between the assertion of HITM# and the first ADS# of the
snoop write-back cycle).
Table 4-12. Various Scenarios of a Snoop Write-Back Cycle Colliding with an On-Going
Cache Fill or Replacement Cycle
Arbi-
tration
Control
Snoop to the Line
That Is Being Filled
Snoop to a Different
Line than the Line
Being Filled
Snoop to the Line
That Is Being
Replaced
Snoop to a Different
Line than the Line
Being Replaced
AHOLD Read all line fill data
into cache line buffer.
Update cache only if
snoop occurred with
INV = 0
No write-back cycle
because the line has
not been modified
yet.
Complete fill if the
cycle is burst. Start
snoop write-back.
If the cycle is non-
burst, the snoop write-
back is reordered
ahead of the line fill.
After the snoop write-
back cycle is
completed, continue
with line fill.
Complete replacement
write-back if the cycle
is burst. Processor
does not initiate a
snoop write-back, but
asserts HITM# until
the replacement write-
back is completed.
If the replacement
cycle is non-burst, the
snoop write-back is re-
ordered ahead of the
replacement write-
back cycle. The
processor does not
continue with the
replacement write-
back cycle.
Complete replacement
write-back if it is a burst
cycle. Initiate snoop
write-back.
If the replacement write-
back is a non-burst cycle,
the snoop write-back
cycle is re-ordered in
front of the replacement
cycle. After the snoop
write-back, the
replacement write-back
is continued from the
interrupt point.
BOFF# Stop reading line fill
data
Wait for BOFF# to be
deasserted.
Continue read from
backed off point
Update cache only if
snoop occurred with
INV = ’0’.
Stop fill
Wait for BOFF# to be
deasserted.
Do snoop write-back
Continue fill from
interrupt point.
Stop replacement
write-back
Wait for BOFF# to be
deasserted.
Initiate snoop write-
back
Processor does not
continue replacement
write-back.
Stop replacement write-
back
Wait for BOFF# to be de-
asserted
Initiate snoop write-back
Continue replacement
write-back from point of
interrupt.
HOLD HOLD is not acknowledged until the current bus cycle (i.e., the line operation) is completed,
except for a non-cacheable, non-burst code prefetch cycle. Consequently there can be no
collision with the snoop cycles using HOLD, except as mentioned earlier. In this case the snoop
write-back is re-ordered ahead of an on-going non-burst, non-cached code prefetch cycle. After
the write-back cycle is completed, the code prefetch cycle continues from the point of interrupt.

Intel Embedded Intel486 Specifications

General

Brand	Intel
Model	Embedded Intel486
Category	Computer Hardware
Language	English