EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
4-24
4.3.3.3 Burst Cacheable Cycles
Figure 4-15 illustrates a burst mode cache fill. As in Figure 4-14, the transfer becomes a cache
line fill when the external system asserts KEN# at the end of the first clock in the cycle.
The external system informs the Intel486 processor that it will burst the line in by asserting
BRDY# at the end of the first cycle in the transfer.
Note that during a burst cycle, ADS# is only driven with the first address.
Figure 4-15. Burst Cacheable Cycle
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CLK
ADS#
A31–A4
M/IO#
D/C#
W/R#
A3–A2
BE3#–BE0#
RDY#
BLAST#
DATA
PCHK#
Ti
To Processor
T1 T2 T2 T2 T2 Ti
KEN#
BRDY#
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