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Intel Embedded Intel486 User Manual

Intel Embedded Intel486
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4-61
BUS OPERATION
tured replacement write-back cycle and is completed under HITM#. However, after AHOLD is
deasserted, the replacement write-back cycle is not completed.
If there is a snoop hit to a line that is different from the one being replaced, the non-burst replace-
ment write-back cycle is fractured, and the snoop write-back cycle is reordered ahead of the re-
placement write-back cycle. After the snoop write-back is completed, the replacement write-back
cycle continues.
4.4.3.4 Snoop under BOFF#
BOFF# is capable of fracturing any transfer, burst or non-burst. The output pins (see Table 4-8
and Table 4-12) of the Write-Back Enhanced IntelDX4 processor are floated in the clock period
following the assertion of BOFF#. If the system snoop hits a modified line using BOFF#, the
snoop write-back cycle is reordered ahead of the current cycle. BOFF# must be de-asserted for
the processor to perform a snoop write-back cycle and resume the fractured cycle. The fractured
cycle resumes with a new ADS# and begins with the first uncompleted transfer. Snoops are per-
mitted under BOFF#, but write-back cycles are not started until BOFF# is de-asserted. Conse-
quently, multiple snoop cycles can occur under a continuously asserted BOFF#, but only up to
the first asserted HITM#.
Snoop under BOFF# during Cache Line Fill
As shown in Figure 4-42, BOFF# fractures the second transfer of a non-burst cache line-fill cycle.
The system begins snooping by driving EADS# and INV in clock six. The assertion of HITM#
in clock eight indicates that the snoop cycle hit a modified line and the cache line is written back
to memory. The assertion of HITM# in clock eight and CACHE# and ADS# in clock ten identi-
fies the beginning of the snoop write-back cycle. ADS# is guaranteed to be asserted no sooner
than two clock periods after the assertion of HITM#. Write-back cycles always use the four-dou-
bleword address sequence of 0-4-8-C (burst or non-burst). The snoop write-back cycle begins
upon the de-assertion of BOFF# with HITM# asserted throughout the duration of the snoop write-
back cycle.
If the snoop cycle hits a line that is different from the line being filled, the cache line fill resumes
after the snoop write-back cycle completes, as shown in Figure 4-42.

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Intel Embedded Intel486 Specifications

General IconGeneral
BrandIntel
ModelEmbedded Intel486
CategoryComputer Hardware
LanguageEnglish

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