7-33
PERIPHERAL SUBSYSTEM
Figure 7-18. Timing of a Posted Write
7.4 DIFFERENCE BETWEEN THE Intel486 DX PROCESSOR FAMILY AND
Intel386 PROCESSORS
The IntelDX2 and IntelDX4 processors are integrated chips that is include a CPU, a math copro-
cessor, and a cache controller. It is fully compatible with its predecessor, the Intel386 DX pro-
cessor, yet has the following differences:
• Intel486 processor offers dynamic bus sizing to support 8-, 16-, and 32-bit bus sizes, except
for the Ultra-Low Power Intel486 GX processor, which supports a 16-bit data bus only.
Dynamic bus sizing requires external swapping logic. The Intel386 DX processor supports
only 16-bit and 32-bit bus sizes and does not require swapping logic.
• The Intel486 processor has a burst transfer mode which can transfer four 32-bit words from
external memory to the on-chip cache using only five clock cycles. The Intel386 DX
processor requires at least eight clock cycles to transfer the same amount of data.
• The Intel486 processor has a BREQ output which supports multi-processor environments.
• The Intel486 processor’s bus is significantly faster than the Intel386 processor’s bus. New
features include a 1x clock, parity support
†
, burst cycles, cacheable cycles, cache invalidate
cycles and 8-bit support. The Hardware Interface and Bus Operation chapters of the
Embedded Intel486™ Processor Family Developer’s Manual explains of the bus
functionality and its hardware interface.
• To support the on-chip cache, new bits have been added to control register 0 (CD and NW),
new pins have been added to the bus, and new bus cycle types have been added. The on-
chip cache must be enabled after reset by clearing the CD and NW bit in CR0.
†
Not available in the ULP486SX or ULP486GX processors.
CLK
T1 T1 T2T2
ADS
CPU
Latched
RDX#
Address
Address
Cycle 1
Cycle 1 Cycle 2
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