Intel Embedded Intel486 User Manual

EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
4-20
Figure 4-12. Non-Cacheable, Non-Burst, Multiple-Cycle Transfers
Each cycle in the transfer begins when ADS# is asserted and the cycle is complete when the ex-
ternal system asserts RDY#.
The Intel486 processor indicates the last cycle of the transfer by asserting BLAST#. The next
RDY# asserted by the external system terminates the transfer.
4.3.2.4 Non-Cacheable Burst Cycles
The external system converts a multiple cycle request into a burst cycle by asserting BRDY# rath-
er than RDY# in the first cycle of the transfer. This is illustrated in Figure 4-13.
There are several features to note in the burst read. ADS# is asserted only during the first cycle
of the transfer. RDY# must be deasserted when BRDY# is asserted.
BLAST# behaves exactly as it does in the non-burst read. BLAST# is deasserted in the second
clock of the first cycle of the transfer, indicating more cycles to follow. In the last cycle, BLAST#
is asserted, prompting the external memory system to end the burst after asserting the next
BRDY#.
CLK
ADS#
A31–A2
M/IO#
D/C#
W/R#
BE3#–BE0#
RDY#
BRDY#
BLAST#
DATA
To Processor
†
KEN#
2nd Data
TiT2T1T2T1Ti
1st Data
†
†
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Intel Embedded Intel486 Specifications

General

Brand	Intel
Model	Embedded Intel486
Category	Computer Hardware
Language	English