4-31
BUS OPERATION
Figure 4-22. Burst Write as a Result of BS8# or BS16#
4.3.6 Locked Cycles
Locked cycles are generated in software for any instruction that performs a read-modify-write op-
eration. During a read-modify-write operation, the Intel486 processor can read and modify a vari-
able in external memory and ensure that the variable is not accessed between the read and write.
Locked cycles are automatically generated during certain bus transfers. The XCHG (exchange)
instruction generates a locked cycle when one of its operands is memory-based. Locked cycles
are generated when a segment or page table entry is updated and during interrupt acknowledge
cycles. Locked cycles are also generated when the LOCK instruction prefix is used with selected
instructions.
Locked cycles are implemented in hardware with the LOCK# pin. When LOCK# is asserted, the
Intel486 processor is performing a read-modify-write operation and the external bus should not
be relinquished until the cycle is complete. Multiple reads or writes can be locked. A locked cycle
is shown in Figure 4-23. LOCK# is asserted with the address and bus definition pins at the begin-
ning of the first read cycle and remains asserted until RDY# is asserted for the last write cycle.
For unaligned 32-bit read-modify-write operations, the LOCK# remains asserted for the entire
duration of the multiple cycle. It deasserts when RDY# is asserted for the last write cycle.
242202–143
CLK
ADS#
BE3#–BE0#
RDY#
BLAST#
DATA
Ti
From Processor
T1 T2 T2 T2 T2 Ti
BS8#
BRDY#
ADDR
SPEC
‡
‡
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