7-51
PERIPHERAL SUBSYSTEM
which will allow connection to 100/10 Mbps networks. For 10 Mbps networks, the 82557 can be
interfaced to a standard ENDEC device (such as the Intel 82503 Serial Interface), while maintain-
ing software compatibility with 100 Mbps solutions.
The 82557 is designed to implement cost effective, high performance PCI add-in adapters, em-
bedded PCs, or other interconnect devices such as hubs or bridges. Its combination of high inte-
gration and low cost make it ideal for these applications.
7.6.2.2 Features and Enhancements
The following list summarizes the main features of the Intel 82557 controller:
• Glueless 32-bit PCI Bus Master Interface (Direct Drive of Bus), compatible with PCI Bus
Specification, Revision 2.1
• 82596-like chained memory structure
• Improved dynamic transmit chaining for enhanced performance
• Programmable transmit threshold for improved bus utilization
• Early receive interrupt for concurrent processing of receive data
• FLASH support up to 1 Mbyte
• Large on-chip receive and transmit FIFOs (3 Kbytes each)
• On-chip counters for network management
• Back-to-back transmit at 100 Mbps
• EEPROM support
• Support for both 10 Mbps and 100 Mbps networks
• Interface to MII-compliant PHY devices, including Intel 82553 Physical Interface
component for 10/100 Mbps designs
• Compatible with IEEE 802.3u 100Base-T, TX, and T4
• Interface to Intel 82503 or other serial device for 10 Mbps designs: Compatible with IEEE
802.3 10Base-T
• Autodetect and autoswitching for 10 or 100 Mbps network speeds
• Capable of full or half duplex at 10 and 100 Mbps
• 160-Lead QFP package
Figure 7-27 shows a high level block diagram of the 82557 part. It is divided into three main sub-
systems: a parallel subsystem, a FIFO subsystem and the 10/100 Mbps CSMA/CD unit.
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