8-31
SYSTEM BUS DESIGN
the cycle type (read or write). Table 15 shows when data swapping is provided during DMA and
ISA master cycles to ISA slaves.
8.4.5.4 Wait-State Generation
The ISA bridge adds wait-states to the following cycles, if IOCHRDY is sampled low (deassert-
ed).
• During Refresh and ISA bridge master cycles (not including DMA) to the ISA bus.
• During DMA-compatible transfers between ISA I/O and ISA memory only.
Wait states are added as long as IOCHRDY remains low.
For ISA master cycles targeted for the ISA bridge’s internal registers or main memory, the ISA
bridge always extends the cycle by driving IOCHDY low until the transaction is complete.
8.4.5.5 Cycle Shortening
The ISA bridge shortens the following cycles, if ZEROWS# is sampled asserted (low).
• During ISA bridge master cycles (not including DMA) to 8-bit and 16-bit ISA memory.
• During ISA bridge master cycles (not including DMA) to 8-bit ISA I/O only.
For ISA master cycles targeted for the ISA bridge’s internal registers or main memory, the ISA
bridge does not assert ZEROWS#. When IOCHRDY and ZEROWS# are sampled low at the
same time, IOCHRDY takes precedence and wait states are added.
Table 8-3. DMA Data Swap
DMA I/O Device
Size
ISA Memory
Slave Size
Swap
Comments
(I/O) ↔ Memory
8-bit 8-bit No SD[7:0]↔SD[7:0]
8-bit 16-bit No SD[7:0]↔SD[7:0]
8-bit 16-bit Yes SD[7:0]↔SD[15:8]
16-bit 8-bit No Not Supported
16-bit 16-bit No SD[15:0]↔SD[15:0]
Table 8-4. 16-bit Master to 8-bit Slave Data Swap
SBHE# SA0 SD[15:8] SD[7:0] Comments
0 0 Odd Even Word Transfer (data swapping not required)
0 1 Odd Odd Byte Swap (1, 2)
1 0 Even Byte Transfer (data swapping not required)
1 1 Not Allowed
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