2-9
INTRODUCTION
of other components should be no more than 50% of the available processor-bus bandwidth. Traf-
fic above 50% degrades performance of the processor.
Figure 2-2. Single-Processor System
Two basic design approaches are used to elaborate the single-processor system into a more com-
plex system. The first approach is to add more devices to the processor bus. This can be done up
to the limit mentioned above: no more than 50% of the processor-bus bandwidth should be used
by devices other than the Intel486 processor. The second design approach is to add more buses
to the system. By adding buses, greater bus bandwidth is created in the system as a whole, which
in turn allows more devices to be added to the system. The two approaches go hand-in-hand to
expand the capabilities of a system. The sections below give only a few examples of the great
variety of designs that are possible with Intel486 processor-compatible devices.
2.4.2 Loosely Coupled Multi-Processor System
Loosely coupled multi-processor systems include board-level products that communicate with
one another through a standard system bus. In this architecture, each board contains a processor
and associated logic. There is typically only one processor per board. Components within each
board communicate on either a processor bus or on the buffered system bus. The system bus usu-
ally provides extra bandwidth beyond the processor bus.
A typical system is shown in Figure 2-3. Such system-bus boards typically occur in higher-end
personal computers and embedded systems that allow for modular expansion. A typical design
would include a coprocessor or LAN interface board in a personal computer, or a network-inter-
face board in a file server or gateway. Systems built from these boards can contain a mix of pro-
cessor types. Devices attached to the processor bus on a given board make demands that may
affect system performance. For example, a typical system may use up to 3% of the bus bandwidth
to handle 10-Mbit/second Ethernet traffic.
Intel486™
Processor
DMA
Controller
Peripheral
Controller
Memory
Processor Bus
Level-2
Cache
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