EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
4-10
4.1.5 Operand Alignment
Physical 4-byte words begin at addresses that are multiples of four. It is possible to transfer a log-
ical operand that spans more than one physical 4-byte word of memory or I/O at the expense of
extra cycles. Examples are 4-byte operands beginning at addresses that are not evenly divisible
by 4, or 2-byte words split between two physical 4-byte words. These are referred to as unaligned
transfers.
Operand alignment and data bus size dictate when multiple bus cycles are required. Table 4-7 de-
scribes the transfer cycles generated for all combinations of logical operand lengths, alignment,
and data bus sizing. When multiple cycles are required to transfer a multibyte logical operand,
the highest-order bytes are transferred first. For example, when the processor executes a 4-byte
unaligned read beginning at byte location 11 in the 4-byte aligned space, the three high-order
bytes are read in the first bus cycle. The low byte is read in a subsequent bus cycle.
Table 4-6. Generating A0, A1 and BHE# from the Intel486™ Processor Byte Enables
BE3# BE2# BE1# BE0#
First Cache Fill Cycle Any Other Cycle
A0 A1 BHE# A0 A1 BHE#
1 110000001
1 100000000
1 000000000
†
0 000000000
1 101000100
1 001000100
†
0 001000100
1 011000011
†
0 011000010
†
0 111000110
KEY:
†
= a non-occurring pattern of Byte Enables; either none are asserted or the pattern has byte
enables asserted for non-contiguous bytes
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