EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
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4.4.3.5 Snoop under HOLD
HOLD can only fracture a non-cacheable, non-burst code prefetch cycle. For all other cycles, the
Write-Back Enhanced IntelDX4 processor does not assert HLDA until the entire current cycle is
completed. If the system snoop hits a modified line under HLDA during a non-cacheable, non-
burstable code prefetch, the snoop write-back cycle is reordered ahead of the fractured cycle. The
fractured non-cacheable, non-burst code prefetch resumes with an ADS# and begins with the first
uncompleted transfer. Snoops are permitted under HLDA, but write-back cycles do not occur un-
til HOLD is de-asserted. Consequently, multiple snoop cycles are permitted under a continuously
asserted HLDA only up to the first asserted HITM#.
Snoop under HOLD during Cache Line Fill
As shown in Figure 4-44, HOLD (asserted in clock two) does not fracture the burst cache line-
fill cycle until the line fill is completed (in clock five). Upon completing the line fill in clock five,
the Write-Back Enhanced IntelDX4 processor asserts HLDA and the system begins snooping by
driving EADS# and INV in the following clock period. The assertion of HITM# in clock nine
indicates that the snoop cycle has hit a modified line and the cache line is written back to memory.
The assertion of HITM# in clock nine and CACHE# and ADS# in clock 11 identifies the begin-
ning of the snoop write-back cycle. The snoop write-back cycle begins upon the de-assertion of
HOLD, and HITM# is asserted throughout the duration of the snoop write-back cycle.
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