EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
4-12
4.2 BUS ARBITRATION LOGIC
Bus arbitration logic is needed with multiple bus masters. Hardware implementations range from
single-master designs to those with multiple masters and DMA devices.
Figure 4-7 shows a simple system in which only one master controls the bus and accesses the
memory and I/O devices. Here, no arbitration is required.
Figure 4-7. Single Master Intel486™ Processor System
Intel486™
Processor
I/O MEM
Control Bus
Data Bus
Address Bus
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