Intel Embedded Intel486 User Manual

EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
4-70
If the processor is in Standard Bus mode, the processor does not issue special acknowledge cycles
in response to the FLUSH# input, although the internal cache is invalidated. The invalidation of
the cache in this case, takes only two bus clocks.
Figure 4-48. Flush Cycle
4.4.6 Pseudo Locked Cycles
In Enhanced Bus mode, PLOCK# is always deasserted for both burst and non-burst cycles.
Hence, it is possible for other bus masters to gain control of the bus during operand transfers that
take more than one bus cycle. A 64-bit aligned operand can be read in one burst cycle or two non-
burst cycles if BS8# and BS16# are not asserted. Figure 4-49 shows a 64-bit floating-point oper-
and or Segment Descriptor read cycle, which is burst by the system asserting BRDY#.
4.4.6.1 Snoop under AHOLD during Pseudo-Locked Cycles
AHOLD can fracture a 64-bit transfer if it is a non-burst cycle. If the 64-bit cycle is burst, as
shown in Figure 4-49, the entire transfer goes to completion and only then does the snoop write-
back cycle start.
242202-160
CLK
ADS#
RDY#
BRDY#
FLUSH#
ADDR
M/IO#
D/C#
W/R#,
BE3–0#
CACHE#
BLAST#
DATA
T1 T1 T2 T2 T2 T2 T1 T1 T2 T1 T2 T1 T1
Write-Back
1st Flush
Acknowledge
2nd Flush
Acknowledge

Intel Embedded Intel486 Specifications

General

Brand	Intel
Model	Embedded Intel486
Category	Computer Hardware
Language	English