EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
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encountered in the program being executed, the prefetch unit gets copies of previously executed
instructions from the cache.
The prefetch unit has the lowest priority for processor bus access. Assuming zero wait-state mem-
ory access, prefetch activity never delays execution. However, if there is no pending data transfer,
prefetching may use bus cycles that would otherwise be idle. The prefetch unit is flushed when-
ever the next instruction needed is not in numerical sequence with the previous instruction; for
example, during jumps, task switches, exceptions, and interrupts.
The prefetch unit never accesses beyond the end of a code segment and it never accesses a page
that is not present. However, prefetching may cause problems for some hardware mechanisms.
For example, prefetching may cause an interrupt when program execution nears the end of mem-
ory. To keep prefetching from reading past a given address, instructions should come no closer
to that address than one byte plus one aligned 16-byte block.
3.5 INSTRUCTION DECODE UNIT
The instruction decode unit receives instructions from the instruction prefetch unit and translates
them in a two-stage process into low-level control signals and microcode entry points, as shown
in Figure 3-1. Most instructions can be decoded at a rate of one per clock. Stage 1 of the decode,
shown in Figure 3-4, initiates a memory access. This allows execution of a two-instruction se-
quence that loads and operates on data in just two clocks, as described in Section 3.2.
The decode unit simultaneously processes instruction prefix bytes, opcodes, modR/M bytes, and
displacements. The outputs include hardwired microinstructions to the segmentation, integer, and
floating-point units. The instruction decode unit is flushed whenever the instruction prefetch unit
is flushed.
3.6 CONTROL UNIT
The control unit interprets the instruction word and microcode entry points received from the in-
struction decode unit. The control unit has outputs with which it controls the integer and floating-
point processing units. It also controls segmentation because segment selection may be specified
by instructions.
The control unit contains the processor’s microcode. Many instructions have only one line of mi-
crocode, so they can execute in an average of one clock cycle. Figure 3-4 shows how execution
fits into the internal pipelining mechanism.
3.7 INTEGER (DATAPATH) UNIT
The integer and datapath unit identifies where data is stored and performs all of the arithmetic
and logical operations available in the Intel386 processor’s instruction set, plus a few new instruc-
tions. It has eight 32-bit general-purpose registers, several specialized registers, an ALU, and a
barrel shifter. Single load, store, addition, subtraction, logic, and shift instructions execute in one
clock.
Two 32-bit bidirectional buses connect the integer and floating-point units. These buses are used
together for transferring 64-bit operands. The same buses also connect the processing units with
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