Intel Embedded Intel486

4-45
BUS OPERATION
AHOLD is asserted, and in the second clock BOFF# is asserted. This guarantees that ADS# is
not floating low. This is necessary only in systems where BOFF# may be asserted in the same
clock as ADS#.
4.3.13 Bus States
A bus state diagram is shown in Figure 4-35. A description of the signals used in the diagram is
given in Table 4-10.
Figure 4-35. Bus State Diagram
240950–069
Ti T1 T2
T1b
T
b
Request Pending
·
HOLD Deasserted
·
AHOLD Deasserted
·
BOFF# Deasserted
(BRDY# · BLAST#) Asserted)
·
HOLD Deasserted
·
AHOLD Deasserted
·
BOFF# Deasserted
AHOLD Deasserted
·
BOFF# Deasserted
·
(HOLD) Deasserted
†
(RDY# Asserted + (BRDY# · BLAST#) Asserted)
·
(HOLD + AHOLD + No Request)
·
BOFF# Deasserted
Request Pending
·
(RDY# Asserted +
B
O
F
F
#
A
s
s
e
r
t
e
d
BOFF#
Deasserted
BOFF#
Asserted
BOFF# Deasserted
BOFF# Asserted
†
HOLD is only factored into this state transition if T
b
was
entered while a non-cacheable. non-burst, code prefetch was
in progress. Otherwise, ignore HOLD.