4-25
BUS OPERATION
4.3.3.4 Effect of Changing KEN# during a Cache Line Fill
KEN# can change multiple times as long as it arrives at its final value in the clock before RDY#
or BRDY# is asserted. This is illustrated in Figure 4-16. Note that the timing of BLAST# follows
that of KEN# by one clock. The Intel486 processor samples KEN# every clock and uses the value
returned in the clock before BRDY# or RDY# to determine if a bus cycle would be a cache line
fill. Similarly, it uses the value of KEN# in the last cycle before early RDY# to load the line just
retrieved from memory into the cache. KEN# is sampled every clock and it must satisfy setup and
hold times.
KEN# can also change multiple times before a burst cycle, as long as it arrives at its final value
one clock before BRDY# or RDY# is asserted.
Figure 4-16. Effect of Changing KEN#
242202-037
CLK
ADS#
A31–A2
M/IO#
D/C#
W/R#
RDY#
BLAST#
DATA
Ti T1 T2 T2
To Processor
T2 T2 T1 T2
A3–A2
BE3#–BE0#
KEN#
†
††
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