Intel Embedded Intel486 User Manual

7-29
PERIPHERAL SUBSYSTEM
7.3 I/O CYCLES
The I/O read and write cycles used in a system are a factor of the I/O control logic implementa-
tion. Figures 7-13 through 7-16 illustrate an I/O read and write cycle for a typical implementation.
7.3.1 Read Cycle Timing
A new processor read cycle is initiated when ADS# is asserted in T1. The address and status sig-
nals (M/IO# = low, W/R# = low, D/C# = high) are asserted. The IOCYC signal is generated by
the control logic by decoding ADS#, M/IO#, W/R# and D/C#. IOCYC indicates to an external
device that an I/O cycle is pending. The IOR# signal is asserted in the T2 state when IOCYC is
valid and RECOV is inactive. The RECOV signal indicates that the new cycle must be delayed
to meet the I/O device recovery time or to prevent data bus contention. The I/O read signal (IOR#)
signal is not asserted until RECOV is deasserted. Data becomes valid after IOR# is asserted, with
the timing dependent on the number of wait states implemented.
In the example, two wait states are required for the slowest I/O device to do a read, and the bus
control logic keeps IOR# active to meet the minimum active time requirement. The worst case
timing values are calculated by assuming maximum delay in the decode logic and through data
transceivers. The following equations show the fastest possible cycle implementation. Wait
States should be added to meet the access times of the I/O devices used. Figure 7-13 and 7-14
show the I/O read cycle timing and the critical analysis.
Figure 7-13. I/O Read Timing Analysis
TR
VD
Read Signal Valid Delay
TR
VD
= T
PLDpd
= 10 ns
TD
SU
Read Data Setup Time
TD
SU
= T
BUFpd
+ T
su
†
= 9 + 5 = 14 ns
TD
HD
Read Data Hold Time
TD
HD
= T
HD
†
– T
BUFpd
= 3 – 9 = –6 ns
†
T
SU
= T
22
= Intel486™ processor time (33 MHz)
T
HD
= Intel486 processor read hold time (33 MHz)

Intel Embedded Intel486 Specifications

General

Brand	Intel
Model	Embedded Intel486
Category	Computer Hardware
Language	English

Summary

Introduction

Processor Features

Details core features like 32-bit RISC core, pipelining, on-chip cache, and MMU.

Memory Management

On-chip Cache

Details the 8/16-Kbyte unified cache, its protocols, and line fills.

Internal Architecture

Instruction Pipelining

Explains how instructions are processed in stages for improved performance.

Bus Interface Unit

Cache Unit

Covers cache operation, including hits, misses, line fills, and update policies.

Floating-Point Unit

Bus Operation

Data Transfer Mechanism

Explains how data operands of various lengths are transferred over the bus.

Dynamic Data Bus Sizing

Bus Arbitration Logic

Bus Functional Description

Locked Cycles

Covers atomic memory access using the LOCK# pin for read-modify-write operations.

Invalidate Cycles

Bus Hold

Enhanced Bus Mode Operation (Write-Back Mode) for the Write-Back Enhanced IntelDX4™ Processor

Describes bus operation changes for write-back mode.

Memory Subsystem Design

The Burst Cycle

The KEN# Input

Improving Write Cycle Latency

Covers techniques like interleaving and write posting to reduce write latency.

Second-Level Cache

Explains the advantages and performance benefits of using an L2 cache.

Peripheral Subsystem

Peripheral/Processor Bus Interface

Dynamic Bus Sizing

Bus Control and Ready Logic

Write Buffers and I/O Cycles

82C59A Interface

System Bus Design

EISA BUS: SYSTEM DESIGN EXAMPLE

PCI BUS: SYSTEM DESIGN EXAMPLE

Introduces the PCI bus, its features, and its implementation in embedded systems.

Performance Considerations

Memory Performance Factors

Instruction Execution Performance

Reviews how Intel486 processors achieve faster instruction execution and compares with earlier processors.

Internal Cache Performance Issues

Analyzes the on-chip cache's organization, size, and impact on performance.

On-Chip Write Buffers

Details the function of write buffers in reducing latency and enhancing write performance.

External Memory Considerations

Second-Level Cache Performance Considerations

Explains the advantages and performance benefits of using an L2 cache.

Floating-Point Performance

Analyzes the floating-point unit's performance, execution sequences, and on-chip interface.

Physical Design and System Debugging

Power Dissipation and Distribution

Discusses power dissipation, capacitive loading, and power/ground planes.

High-Frequency Design Considerations

Covers management of transmission lines, impedance control, and EMI.

Latch-Up

Covers prevention of latch-up by observing voltage limits and using proper layout.

Clock Considerations

Discusses requirements for clock signals, skew, and loading effects.

Thermal Characteristics

Explains thermal specifications, junction temperature calculation, and heatsink usage.

Building and Debugging the Intel486™ Processor-Based System

Outlines steps for building and debugging the system incrementally.

Debugging Features of the Intel486™ Processor

Debug Registers