1-1
CHAPTER 1
GUIDE TO THIS MANUAL
This manual describes the embedded Intel486™ processors. It is intended for use by hardware
designers familiar with the principles of embedded microprocessors and with the Intel486 pro-
cessor architecture.
1.1 MANUAL CONTENTS
This manual contains 10 chapters and an index. This section summarizes the contents of the re-
maining chapters. The remainder of this chapter describes conventions and special terminology
used throughout the manual and provides references to related documentation.
Chapter 2:
“Introduction”
This chapter provides an overview of the current embedded Intel486
processor family, including product features, system components,
system architecture, and applications. This chapter also lists product
frequency, voltage and package offerings.
Chapter 3:
“Internal
Architecture”
This chapter describes the Intel486 processor internal architecture, with
a description of the processor’s functional units.
Chapter 4:
“Bus Operation”
This chapter describes the features of the processor bus, including bus
cycle handling, interrupt and reset signals, cache control, and floating-
point error control.
Chapter 5:
“Memory Subsystem
Design”
This chapter designing a memory subsystem that supports features of
the Intel486 processor such as burst cycles and cache. This chapter also
discusses using write-posting and interleaving to reduce bus cycle
latency.
Chapter 6:
“Cache Subsystem”
This chapter discusses cache theory and the impact of caches on perfor-
mance. This chapter details different cache configurations, including di-
rect-mapped, set associative, and fully associative. In addition, write-
back and write-through methods for updating main memory are de-
scribed.
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