EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
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Chapter 7:
“Peripheral
Subsystem”
This chapter describes the connection of peripheral devices to the
Intel486 processor bus. Design techniques are discussed for interfacing
a variety of devices, including a LAN controller and an interrupt
controller.
Chapter 8:
“System Bus Design”
This chapter provides an overview of system bus design considerations,
including implementing of the EISA and PCI system buses.
Chapter 9:
“Performance
Considerations”
This chapter focuses on the system parameters that affect performance.
External (L2) caches are also examined as a means of improving
memory system performance.
Chapter 10:
“Physical Design and
System Debugging”
The higher clock speeds of Intel486 processor systems require design
guidelines. This chapter outlines basic design considerations, including
power and ground, thermal environment, and system debugging issues.
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