EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
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An example of when a read around could cause a problem follows:
• The interrupt controller is memory-mapped in cacheable memory.
• The write buffer is filled with write cache hits, so a read is reordered in front of the writes.
• One of the pending writes is a write to the interrupt controller control register.
• The read that was reordered (and performed before the write) was to the interrupt
controller’s status register.
Because the reading of the status register occurred before the write to the control register, the
wrong status was read. This can be avoided by not caching memory-mapped I/O devices.
7.2.9 Intel486™ Processor On-Chip Cache Consistency
Some peripheral devices can write to cacheable main memory. If this is the case, cache consis-
tency must be maintained to prevent stale data from being left in the on-chip cache. Cache con-
sistency is maintained by adding bus snooping logic to the system and invalidating any line in the
on-chip cache that another bus master writes to.
Cache line invalidations are usually performed by asserting AHOLD to allow another bus master
to drive the address of the line to be invalidated, and then asserting EADS# to invalidate the line.
Cache line invalidations may also be performed when BOFF# or HOLD is asserted instead of
AHOLD. If AHOLD, BOFF# and HOLD are all deasserted when EADS# is issued, the Intel486
processor invalidates the cache line at the address that happens to be on the bus. Cache line in-
validations and cache consistency are explained more fully in Chapter 6, “Cache Subsystem.”
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