EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
7-20
7.2.1 Bus Control and Ready Logic
A typical peripheral device has address inputs which the processor uses to select the device’s in-
ternal registers. It also has a chip select (CS#) signal which enables it to read data from and write
data to the data bus, as controlled by the READ (RD#) and WRITE (WR#) control signals. For a
processor that has separate memory and I/O addressing, either memory or I/O read and write sig-
nals can be used. As discussed in Section 7.1.1, “Mapping Techniques,” when memory read and
write signals are used to access the peripheral device, the device is called a memory-mapped I/O
device.
Many peripheral devices also generate an interrupt output which is asserted when a response is
required from the processor. Here, the processor must generate an interrupt acknowledge (IN-
TA#) signal.
The bus controller decodes the Intel486 processor’s status outputs (W/R#, M/IO# and D/C#) and
activates command signals according to the type of bus cycle requested.
The bus controller can be used to do the following:
1. Generate an EPROM data read when the control logic generates a signal such as a
memory read command (EPRD#). The command forces the selected memory device to
output data. Chapter 8, “System Bus Design,” provides further explanation.
2. Generate the IOCYC# signal which indicates to the address decoder that a valid I/O cycle
is taking place. As a result, the relevant chip select (CS#) signal should be enabled for the
I/O device. Once IOCYC is generated, the IOR# and IOW# signals are asserted according
to the decoded Intel486 processor status signals (explained later).
3. Initiate I/O read cycles when W/R# is low and M/IO# is low. The I/O read command
(IOR#) is generated. IOR# selects the I/O device which is to output the data.
4. Initiate an I/O write cycle when W/R# is high and M/IO# is low. The I/O write command
signal (IOW#) is generated. This signal instructs a selected I/O device to receive data from
the Intel486 processor.
5. Generate a RECOV signal which is used for recovery and to avoid data contention. This
signal is detailed in Section 7.2.6, “Recovery and Bus Contention.”
6. Generates the interrupt acknowledge signal (INTA#). This signal is sent to the 82C59A
programmable interrupt controller to enable 82C59A interrupt vector data onto the
Intel486 processor data bus using a sequence of interrupt acknowledge pulses that are
issued by the control logic. This signal is detailed in Section 7.5, “Interfacing to x86
Peripherals.”
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