Intel Embedded Intel486 User Manual

EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
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7.2.1 Bus Control and Ready Logic
A typical peripheral device has address inputs which the processor uses to select the device’s in-
ternal registers. It also has a chip select (CS#) signal which enables it to read data from and write
data to the data bus, as controlled by the READ (RD#) and WRITE (WR#) control signals. For a
processor that has separate memory and I/O addressing, either memory or I/O read and write sig-
nals can be used. As discussed in Section 7.1.1, “Mapping Techniques,” when memory read and
write signals are used to access the peripheral device, the device is called a memory-mapped I/O
device.
Many peripheral devices also generate an interrupt output which is asserted when a response is
required from the processor. Here, the processor must generate an interrupt acknowledge (IN-
TA#) signal.
The bus controller decodes the Intel486 processor’s status outputs (W/R#, M/IO# and D/C#) and
activates command signals according to the type of bus cycle requested.
The bus controller can be used to do the following:
1. Generate an EPROM data read when the control logic generates a signal such as a
memory read command (EPRD#). The command forces the selected memory device to
output data. Chapter 8, “System Bus Design,” provides further explanation.
2. Generate the IOCYC# signal which indicates to the address decoder that a valid I/O cycle
is taking place. As a result, the relevant chip select (CS#) signal should be enabled for the
I/O device. Once IOCYC is generated, the IOR# and IOW# signals are asserted according
to the decoded Intel486 processor status signals (explained later).
3. Initiate I/O read cycles when W/R# is low and M/IO# is low. The I/O read command
(IOR#) is generated. IOR# selects the I/O device which is to output the data.
4. Initiate an I/O write cycle when W/R# is high and M/IO# is low. The I/O write command
signal (IOW#) is generated. This signal instructs a selected I/O device to receive data from
the Intel486 processor.
5. Generate a RECOV signal which is used for recovery and to avoid data contention. This
signal is detailed in Section 7.2.6, “Recovery and Bus Contention.”
6. Generates the interrupt acknowledge signal (INTA#). This signal is sent to the 82C59A
programmable interrupt controller to enable 82C59A interrupt vector data onto the
Intel486 processor data bus using a sequence of interrupt acknowledge pulses that are
issued by the control logic. This signal is detailed in Section 7.5, “Interfacing to x86
Peripherals.”

Intel Embedded Intel486 Specifications

General

Brand	Intel
Model	Embedded Intel486
Category	Computer Hardware
Language	English

Summary

Introduction

Processor Features

Details core features like 32-bit RISC core, pipelining, on-chip cache, and MMU.

Memory Management

On-chip Cache

Details the 8/16-Kbyte unified cache, its protocols, and line fills.

Internal Architecture

Instruction Pipelining

Explains how instructions are processed in stages for improved performance.

Bus Interface Unit

Cache Unit

Covers cache operation, including hits, misses, line fills, and update policies.

Floating-Point Unit

Bus Operation

Data Transfer Mechanism

Explains how data operands of various lengths are transferred over the bus.

Dynamic Data Bus Sizing

Bus Arbitration Logic

Bus Functional Description

Locked Cycles

Covers atomic memory access using the LOCK# pin for read-modify-write operations.

Invalidate Cycles

Bus Hold

Enhanced Bus Mode Operation (Write-Back Mode) for the Write-Back Enhanced IntelDX4™ Processor

Describes bus operation changes for write-back mode.

Memory Subsystem Design

The Burst Cycle

The KEN# Input

Improving Write Cycle Latency

Covers techniques like interleaving and write posting to reduce write latency.

Second-Level Cache

Explains the advantages and performance benefits of using an L2 cache.

Peripheral Subsystem

Peripheral/Processor Bus Interface

Dynamic Bus Sizing

Bus Control and Ready Logic

Write Buffers and I/O Cycles

82C59A Interface

System Bus Design

EISA BUS: SYSTEM DESIGN EXAMPLE

PCI BUS: SYSTEM DESIGN EXAMPLE

Introduces the PCI bus, its features, and its implementation in embedded systems.

Performance Considerations

Memory Performance Factors

Instruction Execution Performance

Reviews how Intel486 processors achieve faster instruction execution and compares with earlier processors.

Internal Cache Performance Issues

Analyzes the on-chip cache's organization, size, and impact on performance.

On-Chip Write Buffers

Details the function of write buffers in reducing latency and enhancing write performance.

External Memory Considerations

Second-Level Cache Performance Considerations

Explains the advantages and performance benefits of using an L2 cache.

Floating-Point Performance

Analyzes the floating-point unit's performance, execution sequences, and on-chip interface.

Physical Design and System Debugging

Power Dissipation and Distribution

Discusses power dissipation, capacitive loading, and power/ground planes.

High-Frequency Design Considerations

Covers management of transmission lines, impedance control, and EMI.

Latch-Up

Covers prevention of latch-up by observing voltage limits and using proper layout.

Clock Considerations

Discusses requirements for clock signals, skew, and loading effects.

Thermal Characteristics

Explains thermal specifications, junction temperature calculation, and heatsink usage.

Building and Debugging the Intel486™ Processor-Based System

Outlines steps for building and debugging the system incrementally.

Debugging Features of the Intel486™ Processor

Debug Registers