Intel Embedded Intel486

7-19
PERIPHERAL SUBSYSTEM
Figure 7-9. Basic I/O Interface Block Diagram
Clock
CLK
ADS#
M/IO#
D/C#
W/R#
RDY#
ADS#
M/IO#
D/C#
W/R#
RDY#
Intel486™
CPU
Bus Control
and Ready
IOCYC
EN
Address
Decoder
CS1#
CS0#
INTA
RECOV
IOR#
IOW#
CS0#
CS1#
OE#
Data
Transceiver
DIR
Data
Bus
CS0#
RD#
WR#
A2
I/O #2
(32-Bit)
I/O #1
(32-Bit)
RD#
WR#
A2
CS1#
32
32 32 4
(To Interrupt Controller)
Data
Bus
Addr
Bus
BE3#–
BE0#