EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
7-18
Subsystem Design,” it is necessary to utilize the burst-bus feature of the Intel486 processor for
the DRAM control implementation. The cache subsystem, as described in Chapter 6, “Cache
Subsystem,” also plays an important role in overall system performance. For many systems how-
ever, the on-chip cache provides sufficient performance.
A high-performance Intel486 processor-based system, requires an efficient peripheral subsystem.
This section describes the elements of this system, including the I/O devices on the expansion bus
(the memory bus) and the local I/O bus. In a typical system, a number of slave I/O devices can
be controlled through the same local bus interface. Complex peripheral devices which can act as
bus masters may require a more complex interface.
The bus interface control logic is shown in Figure 7-9 and consists of three main blocks: the bus
control and ready logic, the data transceiver and byte swap logic, and the address decoder.
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