7-49
PERIPHERAL SUBSYSTEM
The CA, 596RESET, and PORT# signals are generated according to the equations shown in Fig-
ure 7-26. The M/IO# and D/C# signals are also generated by the glue logic. When both HOLD
and HLDA are asserted, indicating that the coprocessor has requested and been granted the bus,
M/IO# and D/C# must be driven high.
Figure 7-26. 596RESET, CA, and PORT# Equations
Caching of the coprocessor memory structures in the Intel486 processor internal cache may be
disadvantageous, because these memory structures are not directly executable by the processor.
Typically, most coprocessor bus activity consists of receiving and transmitting frames, managing
the receive frame area, and prefetching descriptor pointers. The system control block is typically
accessed only once by the processor for every update of this area made by the coprocessor. The
processor gains no advantage from caching locations which are used only once. Also, each time
a cached memory location is written to by the coprocessor, a cache invalidation cycle must be
performed.
For systems in which caching is obligatory, external logic must monitor ADS# and W/R# and
drive the EADS# cache invalidation input to the processor.
7.6.1.8 82596 Co-processor Performance
With a 25-MHz clock, the 82596 coprocessor can transfer data at up to 80 Mbyte/second in burst
cycles, or 50 Mbytes/second in non-burst cycles. With a 33-MHz clock, the rates are
106 Mbytes/second for burst and 66 Mbytes/second for non-burst. Most transfers in a Intel486
HLDA
ADDRESS
ADS#
D0
RESET
D/C#, M/IO#
CLK
HOLD
CA
596RESET
PORT#
82596 LAN
Controller
85C220
PLD
CA = (CA Address Decode) & ADS# & D0 Registered
596RESET = (596RESET Address Decode) & D0 I RESET Registered
PORT# = (Port Access Address Decode) & ADS# Combinatorial
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