EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
8-16
Host address bus to EISA LA bus output enable (HALAOE#) is an output signal which enables
the output of the address buffers for host address bus bits 31–2 on to the EISA LA bus bits 31–2.
The signal is asserted during CPU, DMA and refresh cycles along with HALAOE#.
Host address latch enable (HALE#) is an output signal which latches the LA address bus on to
the host address bus. The latch closes on the trailing edge, and the host address bus is held until
the slave terminates the cycle.
EISA LA to EISA SA output enable (LASAOE#) is an output signal which enables the EISA LA
bus bits 19-2 on the EISA SA bus. It is asserted during CPU, EISA bus master, DMA and refresh
cycles.
EISA LA to host address output enable (LAHAOE#) is an output signal which enables address
buffers from the EISA LA bits to the host address bus. It is asserted during EISA/ISA bus master
cycles.
LA latch enable (LALE#) is an output signal which latches the host address bus on to the LA ad-
dress bus. It is useful when the CPU operates in burst mode or when additional address pipelining
is required on the host bus.
EISA SA to EISA LA output enable (SALAOE#) can be used to the output of the address buffers
from the EISA SA bus bits 16-2 on to the EISA LA bus 16–2. It is asserted during ISA bus master
cycles.
SA latch enable (SALE#) is an output signal which latches the LA address bus on to the SA ad-
dress bus. It can be asserted during EISA master, CPU, regular DMA, and DMA burst cycles.
8.3.6.1 Functions of the ISP
The ISP provides system arbitration, DMA control, interrupt control, and counting by using in-
terval timer/counters.
The system arbiter on the ISP evaluates requests from several sources including DMA channels,
EISA devices, refresh requesters, and the host CPU: DREQ is generated by 8-, 16-, or 32-bit de-
vices that require DMA service; MREQ# is generated by 16-bit or 32-bit EISA devices; and
CPUMISS# is generated by the host CPU. Refresh requests are generated internally using the
timers. Request priority is assigned on different levels, and at each level, devices are given rotat-
ing priority. Examples of priorities and assignments are shown in the ISP datasheet. The arbiter
determines which requester receives the bus from EISA masters, DMA slaves, refresh requesters
and the host CPU.
The on-chip DMA controller is functionally equivalent to two 8237 DMA controllers. Seven in-
dependent channels can be programmed. Data widths of 8-, 16-, and 32-bits are supported, as are
ISA-compatible, ISA/EISA compatible, type A/type B modes, and EISA type C mode. Single,
block, demand, or cascade transfer modes are supported. The DMA controller provides refresh
address generation, and buffer chaining.
The ISP provides an ISA-compatible interrupt controller and the functionality of two 8259 inter-
rupt controllers. The ISP can handle fourteen external interrupts and two internal interrupts. The
internal interrupts are for internal functions only and not available externally. A non-maskable
interrupt can be generated by hardware or software.
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