Intel Embedded Intel486 User Manual

8-15
SYSTEM BUS DESIGN
Figure 8-4. EBB Byte Transfer
Copy enable between bytes SDCPYEN(03#–01#, 13#) are output controls that enable the byte
copy transceivers between the EISA bus bytes 0, 1, 2, and 3. Data bits 7–0 can be copied between
data bits 15-8, 23–16 and 31–24. Data bits 15–8 can be copied between data bits 31–24.
Copy up (SDCPYUP) is an output that controls the direction of the byte copy transceivers to copy
the lower bytes to the higher bytes and vice versa.
System (EISA) to host data latch enables (SDHDLE3#–SDHDLE0#) are outputs that control the
latching of data from the EISA bus to the host bus.
System (EISA) data output enable (SDOE2#–SDOE0#) are output enables to data buffers on the
EISA bus.
Host data to system (EISA) data latch enables (HDSDLE1#–HDSDLE0#) are outputs that con-
trol the latching of data from the host data bus to the EISA data bus.
Host data output enables (HDOE1#, HDOE0#) are output enables to the host data bus buffers.
Host Data Bus
EBB
REG
EBB
REG
EBB
REG
EBB
REG
245
245 245 245
EISA/ISA
Data Bus

Intel Embedded Intel486 Specifications

General

Brand	Intel
Model	Embedded Intel486
Category	Computer Hardware
Language	English