4-33
BUS OPERATION
The first cycle of a 64-bit floating-point write is the only case in which both PLOCK# and
BLAST# are asserted. Normally PLOCK# and BLAST# are the inverse of each other.
During all of the cycles in which PLOCK# is asserted, HOLD is not acknowledged until the cycle
completes. This results in a large HOLD latency, especially when BS8# or BS16# is asserted. To
reduce the HOLD latency during these cycles, windows are available between transfers to allow
HOLD to be acknowledged during non-cacheable code prefetches. PLOCK# is asserted because
BLAST# is deasserted, but PLOCK# is ignored and HOLD is recognized during the prefetch.
PLOCK# can change several times during a cycle, settling to its final value in the clock in which
RDY# is asserted.
4.3.7.1 Floating-Point Read and Write Cycles
For IntelDX2 and Write-Back Enhanced IntelDX4 processors, 64-bit floating-point read and
write cycles are also examples of operand transfers that take more than one bus cycle.
Figure 4-24. Pseudo Lock Timing
4.3.8 Invalidate Cycles
Invalidate cycles keep the Intel486 processor internal cache contents consistent with external
memory. The Intel486 processor contains a mechanism for monitoring writes by other devices to
external memory. When the Intel486 processor finds a write to a section of external memory con-
tained in its internal cache, the Intel486 processor’s internal copy is invalidated.
TiT2T1T2T1Ti
CLK
ADS#
A31–A2
M/IO#
D/C#
BE3#–BE0#
W/R#
RDY#
BLAST#
From Processor
DATA
PLOCK#
Write Write
‡
‡
‡
242202-144
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