4-29
BUS OPERATION
The order in which the Intel486 processor requests operands during an interrupted burst transfer
is shown by Table 4-7 on page 4-11. Mixing RDY# and BRDY# does not change the order in
which operand addresses are requested by the Intel486 processor.
An example of the order in which the Intel486 processor requests operands during a cycle in
which the external system mixes RDY# and BRDY# is shown in Figure 4-20. The Intel486 pro-
cessor initially requests a transfer beginning at location 104. The transfer becomes a cache line
fill when the external system asserts KEN#. The first cycle of the cache fill transfers the contents
of location 104 and is terminated with RDY#. The Intel486 processor drives out a new request
(by asserting ADS#) to address 100. If the external system terminates the second cycle with
BRDY#, the Intel486 processor next requests/expects address 10C. The correct order is deter-
mined by the first cycle in the transfer, which may not be the first cycle in the burst if the system
mixes RDY# with BRDY#.
Figure 4-20. Interrupted Burst Cycle with Non-Obvious Order of Addresses
4.3.5 8- and 16-Bit Cycles
The Intel486 processor supports both 16- and 8-bit external buses through the BS16# and BS8#
inputs. BS16# and BS8# allow the external system to specify, on a cycle-by-cycle basis, whether
the addressed component can supply 8, 16 or 32 bits. BS16# and BS8# can be used in burst cycles
as well as non-burst cycles. If both BS16# and BS8# are asserted for any bus cycle, the Intel486
processor responds as if only BS8# is asserted.
242202-068
CLK
ADS#
A31–A2
BRDY#
BLAST#
DATA
Ti T1 T2 Ti
To Processor
T1 T2 T2 T2
KEN#
RDY#
104 100 10C 108
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