EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
4-30
The timing of BS16# and BS8# is the same as that of KEN#. BS16# and BS8# must be asserted
before the first RDY# or BRDY# is asserted. Asserting BS16# and BS8# can force the Intel486
processor to run additional cycles to complete what would have been only a single 32-bit cycle.
BS8# and BS16# may change the state of BLAST# when they force subsequent cycles from the
transfer.
Figure 4-21 shows an example in which BS8# forces the Intel486 processor to run two extra cy-
cles to complete a transfer. The Intel486 processor issues a request for 24 bits of information. The
external system asserts BS8#, indicating that only eight bits of data can be supplied per cycle. The
Intel486 processor issues two extra cycles to complete the transfer.
Figure 4-21. 8-Bit Bus Size Cycle
Extra cycles forced by BS16# and BS8# signals should be viewed as independent bus cycles.
BS16# and BS8# should be asserted for each additional cycle unless the addressed device can
change the number of bytes it can return between cycles. The Intel486 processor deasserts
BLAST# until the last cycle before the transfer is complete.
Refer to Section 4.1.2, “Dynamic Data Bus Sizing,” for the sequencing of addresses when BS8#
or BS16# are asserted.
During burst cycles, BS8# and BS16# operate in the same manner as during non-burst cycles. For
example, a single non-cacheable read could be transferred by the Intel486 processor as four 8-bit
burst data cycles. Similarly, a single 32-bit write could be written as four 8-bit burst data cycles.
An example of a burst write is shown in Figure 4-22. Burst writes can only occur if BS8# or
BS16# is asserted.
242202-069
CLK
ADS#
A31–A2
M/IO#
D/C#
W/R#
RDY#
BLAST#
DATA
Ti T1 T2 Ti
To Processor
T1 T2 T1 T2
BS8#
BE3#–BE0#
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