4-65
BUS OPERATION
Figure 4-44. Snoop under HOLD during Line Fill
If HOLD is asserted during a non-cacheable, non-burst code prefetch cycle, as shown in
Figure 4-45, the Write-Back Enhanced IntelDX4 processor issues HLDA in clock seven (which
is the clock period in which the next RDY# is asserted). If the system snoop hits a modified line,
the snoop write-back cycle begins after HOLD is released. After the snoop write-back cycle is
completed, an ADS# is issued and the code prefetch cycle resumes.
242202-156
CLK
HOLD
HLDA
INV
HITM#
A31–A4
A3–A2
ADS#
1 2 3 4 5 6 7 8 9 10111213141516171819
BLAST#
CACHE#
BRDY#
To Processor
W/R#
0 4 8 C
EADS#
0 4 8 C
Linefill
†
†
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