Intel Embedded Intel486 User Manual

EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
4-62
Figure 4-42. Snoop under BOFF# during a Cache Line-Fill Cycle
An ADS# is always issued when a cycle resumes after being fractured by BOFF#. The address
of the fractured data transfer is reissued under this ADS#, and CACHE# is not issued unless the
fractured operation resumes from the first transfer (e.g., first doubleword). If the system asserts
BOFF# and RDY# simultaneously, as shown in clock four on Figure 4-42, BOFF# dominates and
RDY# is ignored. Consequently, the Write-Back Enhanced IntelDX4 processor accepts only up
to the x4h doubleword, and the line fill resumes with the x0h doubleword. ADS# initiates the re-
sumption of the line-fill operation in clock period 15. HITM# is de-asserted in the clock period
following the clock period in which the last RDY# or BRDY# of the write-back cycle is asserted.
Hence, HITM# is guaranteed to be de-asserted before the ADS# of the next cycle.
242202-154
CLK
BOFF#
EADS#
INV
HITM#
ADS#
BLAST#
To Processor
1 2 3 4 5 6 7 8 91011121314151617181920212223
A31–A4
A3–A2
RDY#
CACHE#
W/R#
BRDY#
Linefill
Write Back Cycle Line Fill Cycle Cont.
40 04C80C8
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Intel Embedded Intel486 Specifications

General

Brand	Intel
Model	Embedded Intel486
Category	Computer Hardware
Language	English