4-53
BUS OPERATION
snoop addresses and asserting EADS#. INV should be driven low during read operations to min-
imize invalidations, and INV should be driven high to invalidate a cache line during write oper-
ations. The Write-Back Enhanced IntelDX4 processor asserts HITM# if the cycle hits a modified
line in the cache. This output signal becomes valid two clock periods after EADS# is valid on the
bus. HITM# remains asserted until the modified line is written back and remains asserted until
the RDY# or BRDY# of the snoop cycle is asserted. Snoop operations could interrupt an ongoing
bus operation in both the Standard Bus and Enhanced Bus modes. The Write-Back Enhanced
IntelDX4 processor can accept EADS# in every clock period while in Standard Bus mode. In En-
hanced Bus mode, the Write-Back Enhanced IntelDX4 processor can accept EADS# every other
clock period or until a snoop hits an M-state line. The Write-Back Enhanced IntelDX4 processor
does not accept any further snoop cycles inputs until the previous snoop write-back operation is
completed.
All write-back cycles adhere to the burst address sequence of 0-4-8-C. The CACHE#, PWT, and
PCD output pins are asserted and the KEN# and WB/WT# input pins are ignored. Write-back cy-
cles can be either burst or non-burst. All write-back operations write 16 bytes of data to memory
corresponding to the modified line that hit during the snoop.
NOTE
Note that the Write-Back Enhanced IntelDX4 processor accepts BS8# and
BS16# line-fill cycles, but not on replacement or snoop-forced write-back
cycles.
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