Intel Embedded Intel486 User Manual

xiii
CONTENTS
FIGURES
Figure Page
7-10 PLD Equations for Basic I/O Control Logic.................................................................7-23
7-11 I/O Address Example .................................................................................................7-24
7-12 Internal Logic and Truth Table of 74S138 ..................................................................7-25
7-13 I/O Read Timing Analysis...........................................................................................7-29
7-14 I/O Read Timings .......................................................................................................7-30
7-15 I/O Write Cycle Timings..............................................................................................7-31
7-16 I/O Write Cycle Timing Analysis .................................................................................7-32
7-17 Posted Write Circuit....................................................................................................7-32
7-18 Timing of a Posted Write............................................................................................7-33
7-19 Intel486™ Processor Interface to the 82C59A...........................................................7-36
7-20 Cascaded Interrupt Controller ....................................................................................7-37
7-21 82596CA Coprocessor Block Diagram.......................................................................7-40
7-22 82596CA Application Example...................................................................................7-41
7-23 82596-to-Processor Interfacing ..................................................................................7-44
7-24 82596 Shared Memory...............................................................................................7-45
7-25 Bus Throttle Timers ....................................................................................................7-48
7-26 596RESET, CA, and PORT# Equations.....................................................................7-49
7-27 Intel 82557 Block Diagram .........................................................................................7-52
8-1 Intel486™ Processor System.......................................................................................8-4
8-2 Block Diagram of EISA Bus Controller (EBC) ..............................................................8-6
8-3 Block Diagram of Integrated System Peripheral (ISP) .................................................8-8
8-4 EBB Byte Transfer......................................................................................................8-15
8-5 Example System Block Diagram ................................................................................8-20
8-6 System Controller Block Diagram...............................................................................8-22
8-7 ISA Bridge Block Diagram..........................................................................................8-23
8-8 Internal DMA Controller..............................................................................................8-34
9-1 Cache Hit Rate for Various Programs ..........................................................................9-6
9-2 Intel486™ Processor Bus Cycle Mix with On-Chip Cache...........................................9-7
9-3 Effect of Wait States on Performance ........................................................................9-10
9-4 Effect of External Bus Utilization versus Wait States .................................................9-11
9-5 L2 Cache Performance Data with One Write Buffer...................................................9-13
9-6 Performance in Interleaved and Non-Interleaved Systems........................................9-15
9-7 Performance in Systems with and without Posted Writes ..........................................9-16
10-1 Reduction in Impedance.............................................................................................10-3
10-2 Typical Power and Ground Trace Layout for Double-Layer Boards...........................10-5
10-3 Decoupling Capacitors ...............................................................................................10-6
10-4 Circuit without Decoupling..........................................................................................10-7
10-5 Decoupling Chip Capacitors.......................................................................................10-8
10-6 Decoupling Leaded Capacitors ..................................................................................10-9
10-7 Micro-Strip Lines ......................................................................................................10-11
10-8 Strip Lines ................................................................................................................10-12
10-9 Overshoot and Undershoot Effects ..........................................................................10-13
10-10 Loaded Transmission Line .......................................................................................10-13
10-11 Lattice Diagram ........................................................................................................10-16

Intel Embedded Intel486 Specifications

General

Brand	Intel
Model	Embedded Intel486
Category	Computer Hardware
Language	English