Intel Embedded Intel486

xv
CONTENTS
TABLES
Table Page
2-1 Product Options............................................................................................................2-4
3-1 Intel486™ Processor Family Functional Units..............................................................3-1
3-2 Cache Configuration Options .....................................................................................3-13
4-1 Byte Enables and Associated Data and Operand Bytes..............................................4-1
4-2 Generating A31–A0 from BE3#–BE0# and A31–A2 ....................................................4-2
4-3 Next Byte Enable Values for BS
x # Cycles ...................................................................4-4
4-4 Data Pins Read with Different Bus Sizes .....................................................................4-5
4-5 Generating A1, BHE# and BLE# for Addressing 16-Bit Devices..................................4-7
4-6 Generating A0, A1 and BHE# from the Intel486™ Processor Byte Enables..............4-10
4-7 Transfer Bus Cycles for Bytes, Words and Dwords ...................................................4-11
4-8 Burst Order (Both Read and Write Bursts).................................................................4-27
4-9 Special Bus Cycle Encoding ......................................................................................4-42
4-10 Bus State Description.................................................................................................4-46
4-11 Snoop Cycles under AHOLD, BOFF#, or HOLD........................................................4-52
4-12 Various Scenarios of a Snoop Write-Back Cycle Colliding with
an On-Going Cache Fill or Replacement Cycle..........................................................4-54
5-1 Access Length of Typical CPU Functions ....................................................................5-2
5-2 Clock Latencies for DRAM Functions...........................................................................5-6
6-1 Level-1 Cache Hit Rates ..............................................................................................6-3
7-1 Next Byte-Enable Values for the BS
x # Cycles.............................................................7-4
7-2 Valid Data Lines for Valid Byte Enable Combinations..................................................7-5
7-3 PLD Input Signals.........................................................................................................7-9
7-4 Equations .....................................................................................................................7-9
7-5 32-Bit to 8-Bit Steering .................................................................................................7-9
7-6 PLD Input Signals.......................................................................................................7-12
7-7 PLD Output Signals....................................................................................................7-12
7-8 Equation .....................................................................................................................7-12
7-9 32-Bit to 16-Bit Bus Swapping Logic Truth Table.......................................................7-12
7-10 32-Bit to 32-Bit Bus Swapping Logic Truth Table.......................................................7-16
7-11 Bus Cycle Definitions .................................................................................................7-21
7-12 82596 Signals.............................................................................................................7-42
7-13 82596 Bus Bandwidth Utilization................................................................................7-50
8-1 AEN
x Decode Table...................................................................................................8-11
8-2 Supported PCI Bus Commands .................................................................................8-27
8-3 DMA Data Swap.........................................................................................................8-31
8-4 16-bit Master to 8-bit Slave Data Swap......................................................................8-31
9-1 Typical Instruction Mix and Execution Times for the Intel486™ Processor..................9-3
9-2 Programs Used ............................................................................................................9-6
9-3 Floating-Point Instruction Execution...........................................................................9-17
10-1 Comparison of Various Termination Techniques .....................................................10-22
10-2 LEN
i Fields ...............................................................................................................10-42