Lenze EVS 9300 series - Actual Phase Integrator (PHDIFF)

Function library
Function blocks
9.2.52 Actual phase integrator (PHDIFF)
9-181
L
EDSVS9332S-D11 EN 3.0
9.2.52 Actual phase integrator (PHDIFF)
Purpose
Deliberate addition of a phase signal to the setpoint phase.
It is also possible to compare setpoint and actual phase signals.
P H D I F F 1
P H D I F F 1 - O U T
P H D I F F 1 - A D D
C 1 2 3 7 / 2
C 1 2 3 2 / 2
P H D I F F 1 - S E T
C 1 2 3 7 / 1
C 1 2 3 2 / 1
P H D I F F 1 - I N
C 1 2 3 6
C 1 2 3 1
C 1 2 3 0 / 1
C 1 2 3 5 / 1
P H D I F F 1 - E N
C 1 2 3 0 / 2
C 1 2 3 5 / 2
P H D I F F 1 - R E S E T
+
-
Fig. 9-136 Actual phase integrator (PHDIFF1)
Signal
Source Note
Name Type DIS DIS format CFG List
PHDIFF1-IN phd C1236 dec [rpm] C1231 4 -
PHDIFF1-SET ph C1237/1 dec [inc] C1232/1 3 -
PHDIFF1-ADD ph C1237/2 dec [inc] C1232/2 3 -
PHDIFF1-EN d C1235/1 bin C1230/1 2 -
PHDIFF1-RESET d C1235/2 bin C1230/2 2 HIGH = sets the actual phase integrator = 0
PHDIFF1-OUT ph - - - - without limit
Function
C1230/1 = HIGH
z The speed signal at PHDIFF1-IN is integrated by the actual phase integrator.
z The phase signal at PHDIFF1-ADD is added to the integrated speed signal.
z The result of the actual phase integrator is subtracted from the phase signal at PHDIFF1-SET.
C1230/1 = LOW
z The speed signal at PHDIFF1-IN is integrated by the actual phase integrator.
z The result of the actual phase integrator is subtracted from the phase signal at PHDIFF1-SET.